DocumentHdrVersion "1.1"
Header (DocumentHdr
packageRefs [
(PackageRef
library "ieee"
unitName "std_logic_1164"
itemName "all"
)
]
)
version "15.1"
appVersion "2002.1b (Build 7)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\CMS_FED\\back_end_fpga\\vhdl"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\CMS_FED\\back_end_fpga\\src\\@d@d@r_conversion\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\CMS_FED\\back_end_fpga\\src\\@d@d@r_conversion\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\CMS_FED\\back_end_fpga\\src"
)
(vvPair
variable "appl"
value "HDL Designer - Pro"
)
(vvPair
variable "d"
value "D:\\CMS_FED\\back_end_fpga\\src\\@d@d@r_conversion"
)
(vvPair
variable "d_logical"
value "D:\\CMS_FED\\back_end_fpga\\src\\DDR_conversion"
)
(vvPair
variable "date"
value "07/15/04"
)
(vvPair
variable "day"
value "Thu"
)
(vvPair
variable "day_long"
value "Thursday"
)
(vvPair
variable "dd"
value "15"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TE2MALDIVES"
)
(vvPair
variable "library"
value "back_end_fpga"
)
(vvPair
variable "library_downstream_LeonardoSpectrum"
value "D:\\CMS_FED\\back_end_fpga\\ls"
)
(vvPair
variable "library_downstream_LeonardoSpectrum(GUI)"
value "D:\\CMS_FED\\back_end_fpga\\ls"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\CMS_FED\\back_end_fpga\\sim"
)
(vvPair
variable "mm"
value "07"
)
(vvPair
variable "month"
value "Jul"
)
(vvPair
variable "month_long"
value "July"
)
(vvPair
variable "p"
value "D:\\CMS_FED\\back_end_fpga\\src\\@d@d@r_conversion\\interface"
)
(vvPair
variable "p_logical"
value "D:\\CMS_FED\\back_end_fpga\\src\\DDR_conversion\\interface"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "time"
value "11:00:37"
)
(vvPair
variable "unit"
value "DDR_conversion"
)
(vvPair
variable "user"
value "st79"
)
(vvPair
variable "version"
value "2002.1b (Build 7)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2004"
)
(vvPair
variable "yy"
value "04"
)
]
)
uid 91,0
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uid 8,0
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uid 4340,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4341,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,21625,15000,22375"
)
n "clk2x"
t "std_logic"
o 33
r 2
st 0
s 0
sf 1
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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xt "16000,21500,17600,22500"
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tm "CptPortNameMgr"
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tm "CptPortTypeMgr"
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st "clk2x                : IN     std_logic  ;
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ps "OnEdgeStrategy"
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ro 90
va (VaSet
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n "data1"
t "std_logic_vector"
b "(7 DOWNTO 0)"
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r 15
st 0
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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ju 2
blo "26000,8300"
tm "CptPortNameMgr"
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xt "13900,8500,26000,9500"
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blo "13900,9300"
tm "CptPortTypeMgr"
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uid 4351,0
va (VaSet
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xt "44000,13600,76500,14400"
st "data1                : OUT    std_logic_vector (7 DOWNTO 0) ;
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)
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uid 4352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4353,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,8625,27750,9375"
)
n "data2"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 8
r 16
st 0
s 0
sf 1
tg (CPTG
uid 4354,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4355,0
va (VaSet
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xt "24200,8500,26000,9500"
st "data2"
ju 2
blo "26000,9300"
tm "CptPortNameMgr"
)
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va (VaSet
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xt "13900,9500,26000,10500"
ju 2
blo "13900,10300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4357,0
va (VaSet
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xt "44000,14400,76500,15200"
st "data2                : OUT    std_logic_vector (7 DOWNTO 0) ;
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)
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uid 4358,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4359,0
ro 90
va (VaSet
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xt "27000,9625,27750,10375"
)
n "data3"
t "std_logic_vector"
b "(7 DOWNTO 0)"
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r 17
st 0
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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uid 4361,0
va (VaSet
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xt "24200,9500,26000,10500"
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tm "CptPortNameMgr"
)
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va (VaSet
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xt "13900,10500,26000,11500"
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blo "13900,11300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4363,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15200,76500,16000"
st "data3                : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
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uid 4364,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4365,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,10625,27750,11375"
)
n "data4"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 8
r 18
st 0
s 0
sf 1
tg (CPTG
uid 4366,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4367,0
va (VaSet
)
xt "24200,10500,26000,11500"
st "data4"
ju 2
blo "26000,11300"
tm "CptPortNameMgr"
)
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uid 4368,0
va (VaSet
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xt "13900,11500,26000,12500"
ju 2
blo "13900,12300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4369,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16000,76500,16800"
st "data4                : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
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uid 4370,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4371,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,11625,27750,12375"
)
n "data5"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 8
r 19
st 0
s 0
sf 1
tg (CPTG
uid 4372,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
)
xt "24200,11500,26000,12500"
st "data5"
ju 2
blo "26000,12300"
tm "CptPortNameMgr"
)
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uid 4374,0
va (VaSet
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xt "13900,12500,26000,13500"
ju 2
blo "13900,13300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4375,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16800,76500,17600"
st "data5                : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
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uid 4376,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4377,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,12625,27750,13375"
)
n "data6"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 8
r 20
st 0
s 0
sf 1
tg (CPTG
uid 4378,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4379,0
va (VaSet
)
xt "24200,12500,26000,13500"
st "data6"
ju 2
blo "26000,13300"
tm "CptPortNameMgr"
)
s (Text
uid 4380,0
va (VaSet
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)
xt "13900,13500,26000,14500"
ju 2
blo "13900,14300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4381,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,17600,76500,18400"
st "data6                : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
*9 (CptPort
uid 4382,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4383,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,13625,27750,14375"
)
n "data7"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 8
r 21
st 0
s 0
sf 1
tg (CPTG
uid 4384,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "24200,13500,26000,14500"
st "data7"
ju 2
blo "26000,14300"
tm "CptPortNameMgr"
)
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va (VaSet
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xt "13900,14500,26000,15500"
ju 2
blo "13900,15300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4387,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18400,76500,19200"
st "data7                : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
*10 (CptPort
uid 4388,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4389,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "27000,14625,27750,15375"
)
n "data8"
t "std_logic_vector"
b "(7 DOWNTO 0)"
m 1
o 8
r 22
st 0
s 0
sf 1
tg (CPTG
uid 4390,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4391,0
va (VaSet
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xt "24200,14500,26000,15500"
st "data8"
ju 2
blo "26000,15300"
tm "CptPortNameMgr"
)
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va (VaSet
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xt "13900,15500,26000,16500"
ju 2
blo "13900,16300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4393,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,19200,76500,20000"
st "data8                : OUT    std_logic_vector (7 DOWNTO 0) ;
"
)
)
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uid 4394,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4395,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,19625,15000,20375"
)
n "FE_enable_reg"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 91
r 1
st 0
s 0
sf 1
tg (CPTG
uid 4396,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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st "FE_enable_reg"
blo "16000,20300"
tm "CptPortNameMgr"
)
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va (VaSet
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xt "16000,20500,28100,21500"
blo "16000,21300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4399,0
va (VaSet
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)
xt "44000,2400,76500,3200"
st "FE_enable_reg        : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*12 (CptPort
uid 4400,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4401,0
ro 90
va (VaSet
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fg "0,65535,0"
)
xt "14250,16625,15000,17375"
)
n "frm_addr_fifo_empty"
t "std_logic"
o 68
r 3
st 0
s 0
sf 1
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4403,0
va (VaSet
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xt "16000,16500,23500,17500"
st "frm_addr_fifo_empty"
blo "16000,17300"
tm "CptPortNameMgr"
)
s (Text
uid 4404,0
va (VaSet
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xt "16000,17500,19100,18500"
blo "16000,18300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4405,0
va (VaSet
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)
xt "44000,4000,67000,4800"
st "frm_addr_fifo_empty  : IN     std_logic  ;
"
)
)
*13 (CptPort
uid 4406,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4407,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
n "mod1_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 69
r 4
st 0
s 0
sf 1
tg (CPTG
uid 4408,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4409,0
va (VaSet
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xt "16000,7500,19600,8500"
st "mod1_data"
blo "16000,8300"
tm "CptPortNameMgr"
)
s (Text
uid 4410,0
va (VaSet
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xt "16000,8500,28100,9500"
blo "16000,9300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4411,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4800,76500,5600"
st "mod1_data            : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
)
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uid 4412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4413,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,8625,15000,9375"
)
n "mod2_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 66
r 5
st 0
s 0
sf 1
tg (CPTG
uid 4414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4415,0
va (VaSet
)
xt "16000,8500,19600,9500"
st "mod2_data"
blo "16000,9300"
tm "CptPortNameMgr"
)
s (Text
uid 4416,0
va (VaSet
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xt "16000,9500,28100,10500"
blo "16000,10300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4417,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5600,76500,6400"
st "mod2_data            : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
)
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ps "OnEdgeStrategy"
shape (Triangle
uid 4419,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,9625,15000,10375"
)
n "mod3_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 71
r 6
st 0
s 0
sf 1
tg (CPTG
uid 4420,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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uid 4421,0
va (VaSet
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xt "16000,9500,19600,10500"
st "mod3_data"
blo "16000,10300"
tm "CptPortNameMgr"
)
s (Text
uid 4422,0
va (VaSet
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xt "16000,10500,28100,11500"
blo "16000,11300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4423,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6400,76500,7200"
st "mod3_data            : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
)
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uid 4424,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4425,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
n "mod4_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 67
r 7
st 0
s 0
sf 1
tg (CPTG
uid 4426,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "16000,10500,19600,11500"
st "mod4_data"
blo "16000,11300"
tm "CptPortNameMgr"
)
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uid 4428,0
va (VaSet
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xt "16000,11500,28100,12500"
blo "16000,12300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4429,0
va (VaSet
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)
xt "44000,7200,76500,8000"
st "mod4_data            : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
)
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uid 4430,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4431,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
n "mod5_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 68
r 8
st 0
s 0
sf 1
tg (CPTG
uid 4432,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4433,0
va (VaSet
)
xt "16000,11500,19600,12500"
st "mod5_data"
blo "16000,12300"
tm "CptPortNameMgr"
)
s (Text
uid 4434,0
va (VaSet
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xt "16000,12500,28100,13500"
blo "16000,13300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 4435,0
va (VaSet
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)
xt "44000,8000,76500,8800"
st "mod5_data            : IN     std_logic_vector (3 DOWNTO 0) ;
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)
)
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uid 4436,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4437,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
n "mod6_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 72
r 9
st 0
s 0
sf 1
tg (CPTG
uid 4438,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4439,0
va (VaSet
)
xt "16000,12500,19600,13500"
st "mod6_data"
blo "16000,13300"
tm "CptPortNameMgr"
)
s (Text
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va (VaSet
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xt "16000,13500,28100,14500"
blo "16000,14300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4441,0
va (VaSet
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)
xt "44000,8800,76500,9600"
st "mod6_data            : IN     std_logic_vector (3 DOWNTO 0) ;
"
)
)
*19 (CptPort
uid 4442,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4443,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
n "mod7_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 73
r 10
st 0
s 0
sf 1
tg (CPTG
uid 4444,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4445,0
va (VaSet
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xt "16000,13500,19600,14500"
st "mod7_data"
blo "16000,14300"
tm "CptPortNameMgr"
)
s (Text
uid 4446,0
va (VaSet
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xt "16000,14500,28100,15500"
blo "16000,15300"
tm "CptPortTypeMgr"
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)
dt (MLText
uid 4447,0
va (VaSet
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ps "CptPortTextPlaceStrategy"
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r 13
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tm "CommentText"
wrapOption 3
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position 1
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shape (Rectangle
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va (VaSet
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text (MLText
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xt "59200,66000,60900,67000"
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shape (Rectangle
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sl 0
va (VaSet
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xt "59000,67000,63000,68000"
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text (MLText
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xt "59200,67000,61500,68000"
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position 1
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shape (Rectangle
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xt "63000,66000,80000,67000"
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oxt "18000,69000,35000,70000"
text (MLText
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va (VaSet
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xt "63200,66000,78500,67000"
st "
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tm "CommentText"
wrapOption 3
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position 1
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shape (GroupingShape
uid 17,0
va (VaSet
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xt "59000,63000,100000,68000"
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LanguageMgr "VhdlLangMgr"
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grid (Grid
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isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
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packageList *37 (PackageList
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textVec [
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uid 49,0
va (VaSet
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blo "0,1000"
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uid 50,0
va (VaSet
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defaultCommentText (CommentText
shape (Rectangle
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va (VaSet
vasetType 1
fg "65280,65280,46080"
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xt "0,0,15000,5000"
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text (MLText
va (VaSet
fg "0,0,32768"
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xt "200,200,1600,1200"
st "
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tm "CommentText"
wrapOption 3
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defaultPanel (Panel
shape (RectFrame
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vasetType 1
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title (TextAssociate
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xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
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parentViewRef (DesignUnitViewRef
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shape (Rectangle
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lineColor "0,32896,0"
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biTextGroup (BiTextGroup
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st "<library>"
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gi *40 (GenericInterface
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text (MLText
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xt "0,12000,0,12000"
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header "Generic Declarations"
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portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
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defaultCptPort (CptPort
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shape (Triangle
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va (VaSet
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n "In0"
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tg (CPTG
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f (Text
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dt (MLText
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defaultCptPortBuffer (CptPort
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tg (CPTG
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tm "CptPortNameMgr"
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dt (MLText
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stg "SymDeclLayoutStrategy"
declLabel (Text
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va (VaSet
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xt "42000,0,49400,1200"
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portLabel (Text
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