DocumentHdrVersion "1.1"
Header (DocumentHdr
packageRefs [
(PackageRef
library "ieee"
unitName "std_logic_1164"
itemName "all"
)
]
)
version "15.1"
appVersion "2002.1b (Build 7)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\CMS_FED\\back_end_fpga\\vhdl"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\CMS_FED\\back_end_fpga\\src\\qdr_sram_interface\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\CMS_FED\\back_end_fpga\\src\\qdr_sram_interface\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\CMS_FED\\back_end_fpga\\src"
)
(vvPair
variable "appl"
value "HDL Designer - Pro"
)
(vvPair
variable "d"
value "D:\\CMS_FED\\back_end_fpga\\src\\qdr_sram_interface"
)
(vvPair
variable "d_logical"
value "D:\\CMS_FED\\back_end_fpga\\src\\qdr_sram_interface"
)
(vvPair
variable "date"
value "03/04/04"
)
(vvPair
variable "day"
value "Thu"
)
(vvPair
variable "day_long"
value "Thursday"
)
(vvPair
variable "dd"
value "04"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TE2MALDIVES"
)
(vvPair
variable "library"
value "back_end_fpga"
)
(vvPair
variable "library_downstream_LeonardoSpectrum"
value "D:\\CMS_FED\\back_end_fpga\\ls"
)
(vvPair
variable "library_downstream_LeonardoSpectrum(GUI)"
value "D:\\CMS_FED\\back_end_fpga\\ls"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\CMS_FED\\back_end_fpga\\sim"
)
(vvPair
variable "mm"
value "03"
)
(vvPair
variable "month"
value "Mar"
)
(vvPair
variable "month_long"
value "March"
)
(vvPair
variable "p"
value "D:\\CMS_FED\\back_end_fpga\\src\\qdr_sram_interface\\interface"
)
(vvPair
variable "p_logical"
value "D:\\CMS_FED\\back_end_fpga\\src\\qdr_sram_interface\\interface"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "time"
value "10:47:30"
)
(vvPair
variable "unit"
value "qdr_sram_interface"
)
(vvPair
variable "user"
value "st79"
)
(vvPair
variable "version"
value "2002.1b (Build 7)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2004"
)
(vvPair
variable "yy"
value "04"
)
]
)
uid 136,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 6043,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6044,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,25625,15000,26375"
)
n "clk2x"
t "std_logic"
o 33
r 1
st 0
s 0
sf 1
tg (CPTG
uid 6045,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6046,0
va (VaSet
)
xt "16000,25500,17600,26500"
st "clk2x"
blo "16000,26300"
tm "CptPortNameMgr"
)
s (Text
uid 6047,0
va (VaSet
isHidden 1
)
xt "16000,26500,19100,27500"
blo "16000,27300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6048,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2400,66500,3200"
st "clk2x               : IN     std_logic  ;
"
)
)
*3 (CptPort
uid 6049,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6050,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,32625,15000,33375"
)
n "fe_data"
t "std_logic_vector"
b "(63 DOWNTO 0)"
o 8
r 2
st 0
s 0
sf 1
tg (CPTG
uid 6051,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6052,0
va (VaSet
)
xt "16000,32500,18400,33500"
st "fe_data"
blo "16000,33300"
tm "CptPortNameMgr"
)
s (Text
uid 6053,0
va (VaSet
isHidden 1
)
xt "16000,33500,28500,34500"
blo "16000,34300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6054,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3200,76500,4000"
st "fe_data             : IN     std_logic_vector (63 DOWNTO 0) ;
"
)
)
*4 (CptPort
uid 6055,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6056,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,19625,15000,20375"
)
n "internal_freeze_bar"
t "std_logic"
o 73
r 3
st 0
s 0
sf 1
tg (CPTG
uid 6057,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6058,0
va (VaSet
)
xt "16000,19500,23300,20500"
st "internal_freeze_bar"
blo "16000,20300"
tm "CptPortNameMgr"
)
s (Text
uid 6059,0
va (VaSet
isHidden 1
)
xt "16000,20500,19100,21500"
blo "16000,21300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6060,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4000,66500,4800"
st "internal_freeze_bar : IN     std_logic  ;
"
)
)
*5 (CptPort
uid 6061,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6062,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,23625,15000,24375"
)
n "locked_all_clks"
t "std_logic"
o 64
r 4
st 0
s 0
sf 1
tg (CPTG
uid 6063,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6064,0
va (VaSet
)
xt "16000,23500,21800,24500"
st "locked_all_clks"
blo "16000,24300"
tm "CptPortNameMgr"
)
s (Text
uid 6065,0
va (VaSet
isHidden 1
)
xt "16000,24500,19100,25500"
blo "16000,25300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6066,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4800,66500,5600"
st "locked_all_clks     : IN     std_logic  ;
"
)
)
*6 (CptPort
uid 6067,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6068,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
n "qdr_1_q"
t "std_logic_vector"
b "(17 DOWNTO 0)"
o 12
r 5
st 0
s 0
sf 1
tg (CPTG
uid 6069,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6070,0
va (VaSet
)
xt "16000,14500,18900,15500"
st "qdr_1_q"
blo "16000,15300"
tm "CptPortNameMgr"
)
s (Text
uid 6071,0
va (VaSet
isHidden 1
)
xt "16000,15500,28500,16500"
blo "16000,16300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6072,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5600,76500,6400"
st "qdr_1_q             : IN     std_logic_vector (17 DOWNTO 0) ;
"
)
)
*7 (CptPort
uid 6073,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6074,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
n "qdr_2_q"
t "std_logic_vector"
b "(17 DOWNTO 0)"
o 13
r 6
st 0
s 0
sf 1
tg (CPTG
uid 6075,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6076,0
va (VaSet
)
xt "16000,15500,18900,16500"
st "qdr_2_q"
blo "16000,16300"
tm "CptPortNameMgr"
)
s (Text
uid 6077,0
va (VaSet
isHidden 1
)
xt "16000,16500,28500,17500"
blo "16000,17300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6078,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6400,76500,7200"
st "qdr_2_q             : IN     std_logic_vector (17 DOWNTO 0) ;
"
)
)
*8 (CptPort
uid 6079,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6080,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,12625,28750,13375"
)
n "qdr_addr"
t "std_logic_vector"
b "(18 DOWNTO 1)"
m 1
o 64
r 13
st 0
s 0
sf 1
tg (CPTG
uid 6081,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6082,0
va (VaSet
)
xt "23900,12500,27000,13500"
st "qdr_addr"
ju 2
blo "27000,13300"
tm "CptPortNameMgr"
)
s (Text
uid 6083,0
va (VaSet
isHidden 1
)
xt "14500,13500,27000,14500"
ju 2
blo "14500,14300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6084,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12000,76500,12800"
st "qdr_addr            : OUT    std_logic_vector (18 DOWNTO 1) ;
"
)
)
*9 (CptPort
uid 6085,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6086,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,9625,28750,10375"
)
n "qdr_bw_n"
t "std_logic_vector"
b "(1 DOWNTO 0)"
m 1
o 19
r 14
st 0
s 0
sf 1
tg (CPTG
uid 6087,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6088,0
va (VaSet
)
xt "23700,9500,27000,10500"
st "qdr_bw_n"
ju 2
blo "27000,10300"
tm "CptPortNameMgr"
)
s (Text
uid 6089,0
va (VaSet
isHidden 1
)
xt "14900,10500,27000,11500"
ju 2
blo "14900,11300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6090,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12800,76000,13600"
st "qdr_bw_n            : OUT    std_logic_vector (1 DOWNTO 0) ;
"
)
)
*10 (CptPort
uid 6091,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6092,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,14625,28750,15375"
)
n "qdr_data_in"
t "std_logic_vector"
b "(71 DOWNTO 0)"
m 1
o 67
r 15
st 0
s 0
sf 1
tg (CPTG
uid 6093,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6094,0
va (VaSet
)
xt "22200,14500,27000,15500"
st "qdr_data_in"
ju 2
blo "27000,15300"
tm "CptPortNameMgr"
)
s (Text
uid 6095,0
va (VaSet
isHidden 1
)
xt "14500,15500,27000,16500"
ju 2
blo "14500,16300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6096,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13600,76500,14400"
st "qdr_data_in         : OUT    std_logic_vector (71 DOWNTO 0) ;
"
)
)
*11 (CptPort
uid 6097,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6098,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,16625,28750,17375"
)
n "qdr_data_in_en"
t "std_logic"
m 1
o 86
r 16
st 0
s 0
sf 1
tg (CPTG
uid 6099,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6100,0
va (VaSet
)
xt "21000,16500,27000,17500"
st "qdr_data_in_en"
ju 2
blo "27000,17300"
tm "CptPortNameMgr"
)
s (Text
uid 6101,0
va (VaSet
isHidden 1
)
xt "23900,17500,27000,18500"
ju 2
blo "23900,18300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6102,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14400,66500,15200"
st "qdr_data_in_en      : OUT    std_logic  ;
"
)
)
*12 (CptPort
uid 6103,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6104,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
n "qdr_rd_addr"
t "std_logic_vector"
b "(18 DOWNTO 1)"
o 10
r 7
st 0
s 0
sf 1
tg (CPTG
uid 6105,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6106,0
va (VaSet
)
xt "16000,7500,21000,8500"
st "qdr_rd_addr"
blo "16000,8300"
tm "CptPortNameMgr"
)
s (Text
uid 6107,0
va (VaSet
isHidden 1
)
xt "16000,8500,28500,9500"
blo "16000,9300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6108,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7200,76500,8000"
st "qdr_rd_addr         : IN     std_logic_vector (18 DOWNTO 1) ;
"
)
)
*13 (CptPort
uid 6109,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6110,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,6625,15000,7375"
)
n "qdr_rd_addr_en"
t "std_logic"
o 36
r 8
st 0
s 0
sf 1
tg (CPTG
uid 6111,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6112,0
va (VaSet
)
xt "16000,6500,22200,7500"
st "qdr_rd_addr_en"
blo "16000,7300"
tm "CptPortNameMgr"
)
s (Text
uid 6113,0
va (VaSet
isHidden 1
)
xt "16000,7500,19100,8500"
blo "16000,8300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6114,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8000,66500,8800"
st "qdr_rd_addr_en      : IN     std_logic  ;
"
)
)
*14 (CptPort
uid 6115,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6116,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,8625,28750,9375"
)
n "qdr_read_b"
t "std_logic"
m 1
o 18
r 17
st 0
s 0
sf 1
tg (CPTG
uid 6117,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6118,0
va (VaSet
)
xt "22300,8500,27000,9500"
st "qdr_read_b"
ju 2
blo "27000,9300"
tm "CptPortNameMgr"
)
s (Text
uid 6119,0
va (VaSet
isHidden 1
)
xt "23900,9500,27000,10500"
ju 2
blo "23900,10300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6120,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15200,66500,16000"
st "qdr_read_b          : OUT    std_logic  ;
"
)
)
*15 (CptPort
uid 6121,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6122,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,16625,15000,17375"
)
n "qdr_test_data_en"
t "std_logic_vector"
b "(1 DOWNTO 0)"
o 95
r 9
st 0
s 0
sf 1
tg (CPTG
uid 6123,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6124,0
va (VaSet
)
xt "16000,16500,22600,17500"
st "qdr_test_data_en"
blo "16000,17300"
tm "CptPortNameMgr"
)
s (Text
uid 6125,0
va (VaSet
isHidden 1
)
xt "16000,17500,28100,18500"
blo "16000,18300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6126,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8800,76000,9600"
st "qdr_test_data_en    : IN     std_logic_vector (1 DOWNTO 0) ;
"
)
)
*16 (CptPort
uid 6127,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6128,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
n "qdr_wr_addr"
t "std_logic_vector"
b "(18 DOWNTO 1)"
o 10
r 10
st 0
s 0
sf 1
tg (CPTG
uid 6129,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6130,0
va (VaSet
)
xt "16000,10500,21100,11500"
st "qdr_wr_addr"
blo "16000,11300"
tm "CptPortNameMgr"
)
s (Text
uid 6131,0
va (VaSet
isHidden 1
)
xt "16000,11500,28500,12500"
blo "16000,12300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6132,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9600,76500,10400"
st "qdr_wr_addr         : IN     std_logic_vector (18 DOWNTO 1) ;
"
)
)
*17 (CptPort
uid 6133,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6134,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,9625,15000,10375"
)
n "qdr_wr_addr_en"
t "std_logic"
o 36
r 11
st 0
s 0
sf 1
tg (CPTG
uid 6135,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6136,0
va (VaSet
)
xt "16000,9500,22300,10500"
st "qdr_wr_addr_en"
blo "16000,10300"
tm "CptPortNameMgr"
)
s (Text
uid 6137,0
va (VaSet
isHidden 1
)
xt "16000,10500,19100,11500"
blo "16000,11300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6138,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10400,66500,11200"
st "qdr_wr_addr_en      : IN     std_logic  ;
"
)
)
*18 (CptPort
uid 6139,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6140,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,7625,28750,8375"
)
n "qdr_write_b"
t "std_logic"
m 1
o 17
r 18
st 0
s 0
sf 1
tg (CPTG
uid 6141,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6142,0
va (VaSet
)
xt "22200,7500,27000,8500"
st "qdr_write_b"
ju 2
blo "27000,8300"
tm "CptPortNameMgr"
)
s (Text
uid 6143,0
va (VaSet
isHidden 1
)
xt "23900,8500,27000,9500"
ju 2
blo "23900,9300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6144,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16000,66500,16800"
st "qdr_write_b         : OUT    std_logic  ;
"
)
)
*19 (CptPort
uid 6145,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6146,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,26625,15000,27375"
)
n "reset"
t "std_logic"
o 11
r 12
st 0
s 0
sf 1
tg (CPTG
uid 6147,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6148,0
va (VaSet
)
xt "16000,26500,17700,27500"
st "reset"
blo "16000,27300"
tm "CptPortNameMgr"
)
s (Text
uid 6149,0
va (VaSet
isHidden 1
)
xt "16000,27500,19100,28500"
blo "16000,28300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 6150,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11200,66500,12000"
st "reset               : IN     std_logic  ;
"
)
)
*20 (CptPort
uid 6151,0
ps "OnEdgeStrategy"
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