DocumentHdrVersion "1.1"
Header (DocumentHdr
packageRefs [
(PackageRef
library "ieee"
unitName "std_logic_1164"
itemName "all"
)
]
)
version "15.1"
appVersion "2002.1b (Build 7)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\vhdl"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src\\tst_fe_data_block\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src\\tst_fe_data_block\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src"
)
(vvPair
variable "appl"
value "HDL Designer - Pro"
)
(vvPair
variable "d"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src\\tst_fe_data_block"
)
(vvPair
variable "d_logical"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src\\tst_fe_data_block"
)
(vvPair
variable "date"
value "10/31/03"
)
(vvPair
variable "day"
value "Fri"
)
(vvPair
variable "day_long"
value "Friday"
)
(vvPair
variable "dd"
value "31"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TE2BELIZE"
)
(vvPair
variable "library"
value "back_end_fpga"
)
(vvPair
variable "library_downstream_LeonardoSpectrum"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\ls"
)
(vvPair
variable "library_downstream_LeonardoSpectrum(GUI)"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\ls"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\sim"
)
(vvPair
variable "mm"
value "10"
)
(vvPair
variable "month"
value "Oct"
)
(vvPair
variable "month_long"
value "October"
)
(vvPair
variable "p"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src\\tst_fe_data_block\\interface"
)
(vvPair
variable "p_logical"
value "D:\\CMS_FED\\BE_FPGA_firmware\\back_end_fpga\\src\\tst_fe_data_block\\interface"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "time"
value "12:08:50"
)
(vvPair
variable "unit"
value "tst_fe_data_block"
)
(vvPair
variable "user"
value "st79"
)
(vvPair
variable "version"
value "2002.1b (Build 7)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2003"
)
(vvPair
variable "yy"
value "03"
)
]
)
uid 51,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 1267,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1268,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,31625,28750,32375"
)
n "clk"
t "std_logic"
m 2
o 105
r 21
d 0
s 0
sf 1
tg (CPTG
uid 1269,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1270,0
va (VaSet
font "arial,8,0"
)
xt "26100,31500,27000,32500"
st "clk"
ju 2
blo "27000,32300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1271,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,18400,65000,19200"
st "clk                 : INOUT  std_logic 
"
)
)
*3 (CptPort
uid 1272,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1273,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,17625,15000,18375"
)
n "fe_config_in"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 33
r 3
d 0
s 0
sf 1
tg (CPTG
uid 1274,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1275,0
va (VaSet
font "arial,8,0"
)
xt "16000,17500,23500,18500"
st "fe_config_in : (8:1)"
blo "16000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1276,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4000,76000,4800"
st "fe_config_in        : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*4 (CptPort
uid 1277,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1278,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,25625,28750,26375"
)
n "fe_config_out"
t "std_logic_vector"
b "(8 DOWNTO 1)"
m 1
o 78
r 9
d 0
s 0
sf 1
tg (CPTG
uid 1279,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1280,0
va (VaSet
font "arial,8,0"
)
xt "19100,25500,27000,26500"
st "fe_config_out : (8:1)"
ju 2
blo "27000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1281,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8800,76000,9600"
st "fe_config_out       : OUT    std_logic_vector (8 DOWNTO 1) ;
"
)
)
*5 (CptPort
uid 1282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,19625,15000,20375"
)
n "fe_frame_sync_in"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 1
r 4
d 0
s 0
sf 1
tg (CPTG
uid 1284,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1285,0
va (VaSet
font "arial,8,0"
)
xt "16000,19500,25200,20500"
st "fe_frame_sync_in : (8:1)"
blo "16000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1286,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4800,76000,5600"
st "fe_frame_sync_in    : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*6 (CptPort
uid 1287,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1288,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,23625,28750,24375"
)
n "fe_frame_sync_out"
t "std_logic_vector"
b "(8 DOWNTO 1)"
m 1
o 77
r 10
d 0
s 0
sf 1
tg (CPTG
uid 1289,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1290,0
va (VaSet
font "arial,8,0"
)
xt "17400,23500,27000,24500"
st "fe_frame_sync_out : (8:1)"
ju 2
blo "27000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1291,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9600,76000,10400"
st "fe_frame_sync_out   : OUT    std_logic_vector (8 DOWNTO 1) ;
"
)
)
*7 (CptPort
uid 1292,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1293,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
n "FE_lvds_clk"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 120
r 1
d 0
s 0
sf 1
tg (CPTG
uid 1294,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1295,0
va (VaSet
font "arial,8,0"
)
xt "16000,13500,23000,14500"
st "FE_lvds_clk : (8:1)"
blo "16000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1296,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2400,76000,3200"
st "FE_lvds_clk         : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*8 (CptPort
uid 1297,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1298,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
n "FE_lvds_clk_B"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 119
r 2
d 0
s 0
sf 1
tg (CPTG
uid 1299,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1300,0
va (VaSet
font "arial,8,0"
)
xt "16000,14500,24300,15500"
st "FE_lvds_clk_B : (8:1)"
blo "16000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1301,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3200,76000,4000"
st "FE_lvds_clk_B       : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*9 (CptPort
uid 1302,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1303,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,21625,15000,22375"
)
n "fe_monitor_in"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 3
r 5
d 0
s 0
sf 1
tg (CPTG
uid 1304,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1305,0
va (VaSet
font "arial,8,0"
)
xt "16000,21500,23900,22500"
st "fe_monitor_in : (8:1)"
blo "16000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1306,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5600,76000,6400"
st "fe_monitor_in       : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*10 (CptPort
uid 1307,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1308,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,27625,28750,28375"
)
n "fe_monitor_out"
t "std_logic_vector"
b "(8 DOWNTO 1)"
m 1
o 79
r 11
d 0
s 0
sf 1
tg (CPTG
uid 1309,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1310,0
va (VaSet
font "arial,8,0"
)
xt "18700,27500,27000,28500"
st "fe_monitor_out : (8:1)"
ju 2
blo "27000,28300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1311,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10400,76000,11200"
st "fe_monitor_out      : OUT    std_logic_vector (8 DOWNTO 1) ;
"
)
)
*11 (CptPort
uid 1312,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1313,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,23625,15000,24375"
)
n "fe_readout_sync_in"
t "std_logic_vector"
b "(8 DOWNTO 1)"
o 7
r 6
d 0
s 0
sf 1
tg (CPTG
uid 1314,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1315,0
va (VaSet
font "arial,8,0"
)
xt "16000,23500,25800,24500"
st "fe_readout_sync_in : (8:1)"
blo "16000,24300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1316,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6400,76000,7200"
st "fe_readout_sync_in  : IN     std_logic_vector (8 DOWNTO 1) ;
"
)
)
*12 (CptPort
uid 1317,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1318,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,29625,28750,30375"
)
n "fe_readout_sync_out"
t "std_logic_vector"
b "(8 DOWNTO 1)"
m 1
o 82
r 12
d 0
s 0
sf 1
tg (CPTG
uid 1319,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1320,0
va (VaSet
font "arial,8,0"
)
xt "16800,29500,27000,30500"
st "fe_readout_sync_out : (8:1)"
ju 2
blo "27000,30300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1321,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11200,76000,12000"
st "fe_readout_sync_out : OUT    std_logic_vector (8 DOWNTO 1) ;
"
)
)
*13 (CptPort
uid 1322,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1323,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,25625,15000,26375"
)
n "iclk_1x"
t "std_logic"
o 97
r 7
d 0
s 0
sf 1
tg (CPTG
uid 1324,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1325,0
va (VaSet
font "arial,8,0"
)
xt "16000,25500,18200,26500"
st "iclk_1x"
blo "16000,26300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1326,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7200,66500,8000"
st "iclk_1x             : IN     std_logic  ;
"
)
)
*14 (CptPort
uid 1327,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1328,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,7625,28750,8375"
)
n "mod1_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 89
r 13
d 0
s 0
sf 1
tg (CPTG
uid 1329,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1330,0
va (VaSet
font "arial,8,0"
)
xt "20400,7500,27000,8500"
st "mod1_data : (3:0)"
ju 2
blo "27000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1331,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12000,76000,12800"
st "mod1_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*15 (CptPort
uid 1332,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1333,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,9625,28750,10375"
)
n "mod2_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 90
r 14
d 0
s 0
sf 1
tg (CPTG
uid 1334,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1335,0
va (VaSet
font "arial,8,0"
)
xt "20400,9500,27000,10500"
st "mod2_data : (3:0)"
ju 2
blo "27000,10300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1336,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12800,76000,13600"
st "mod2_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*16 (CptPort
uid 1337,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1338,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,11625,28750,12375"
)
n "mod3_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 91
r 15
d 0
s 0
sf 1
tg (CPTG
uid 1339,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1340,0
va (VaSet
font "arial,8,0"
)
xt "20400,11500,27000,12500"
st "mod3_data : (3:0)"
ju 2
blo "27000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1341,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13600,76000,14400"
st "mod3_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*17 (CptPort
uid 1342,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1343,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,13625,28750,14375"
)
n "mod4_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 92
r 16
d 0
s 0
sf 1
tg (CPTG
uid 1344,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1345,0
va (VaSet
font "arial,8,0"
)
xt "20400,13500,27000,14500"
st "mod4_data : (3:0)"
ju 2
blo "27000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1346,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14400,76000,15200"
st "mod4_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*18 (CptPort
uid 1347,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1348,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,15625,28750,16375"
)
n "mod5_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 93
r 17
d 0
s 0
sf 1
tg (CPTG
uid 1349,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1350,0
va (VaSet
font "arial,8,0"
)
xt "20400,15500,27000,16500"
st "mod5_data : (3:0)"
ju 2
blo "27000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1351,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15200,76000,16000"
st "mod5_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*19 (CptPort
uid 1352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1353,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,17625,28750,18375"
)
n "mod6_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 94
r 18
d 0
s 0
sf 1
tg (CPTG
uid 1354,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1355,0
va (VaSet
font "arial,8,0"
)
xt "20400,17500,27000,18500"
st "mod6_data : (3:0)"
ju 2
blo "27000,18300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1356,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16000,76000,16800"
st "mod6_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*20 (CptPort
uid 1357,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1358,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,19625,28750,20375"
)
n "mod7_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 95
r 19
d 0
s 0
sf 1
tg (CPTG
uid 1359,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1360,0
va (VaSet
font "arial,8,0"
)
xt "20400,19500,27000,20500"
st "mod7_data : (3:0)"
ju 2
blo "27000,20300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1361,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,16800,76000,17600"
st "mod7_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*21 (CptPort
uid 1362,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1363,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "28000,21625,28750,22375"
)
n "mod8_data"
t "std_logic_vector"
b "(3 DOWNTO 0)"
m 1
o 96
r 20
d 0
s 0
sf 1
tg (CPTG
uid 1364,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1365,0
va (VaSet
font "arial,8,0"
)
xt "20400,21500,27000,22500"
st "mod8_data : (3:0)"
ju 2
blo "27000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1366,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,17600,76000,18400"
st "mod8_data           : OUT    std_logic_vector (3 DOWNTO 0) ;
"
)
)
*22 (CptPort
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ps "OnEdgeStrategy"
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